Visualisation in Circuit Design

This event may not be open to the public. Please enquire at the School Office if you wish to attend.

Location: The Butter, Merz Court
Time/Date: 12th May 2010, 13:00

Visualisation techniques can enhance the understanding of circuit behaviour and their operating environment. Visualisation enables exploration of massive quantities of data from a high-level overview right down to low-level detail. I will present some short animated movies that address clock domain crossing circuits, and whole-chip clock distribution. These visualisation aids are used to tune and debug designs, and have uncovered problems not found by the standard development tools.

Published: 12th April 2010