State-of-the-art multi-processor system-on-chips use on-chip networks as their communication fabric. Although most of current on-chip networks are implemented synchronously, asynchronous quasi-delay-insensitive (QDI) on-chip networks have several advantages over their synchronous counterparts. Timing division multiplexing (TDM) flow control methods have been utilized in asynchronous on-chip networks extensively. The data synchronization required by TDM leads to significant speed penalty. Compared with using TDM methods, exploring spatial parallelism and applying the spatial division multiplexing (SDM) flow control method achieve better network throughput with less area overhead. Channel slicing is a pipeline structure that alleviates the speed penalty by removing the synchronization among bit-level data pipelines. SDM is a flow control method that improves network throughput without introducing synchronization among buffers of different frames, which is required by TDM methods on the contrary. The major design problem of SDM is the area consuming crossbars. A novel 2-stage Clos switch structure is proposed to replace the crossbar in SDM routers, which reduces the area overhead significantly. This Clos switch is dynamically reconfigured by a new asynchronous dispatching algorithm.
An asynchronous SDM router is implemented using these new techniques. An asynchronous router using VC is also reproduced for comparison. Performance analyses show that the SDM router outperforms the VC router in throughput, area to throughput efficiency and power to throughput efficiency.
published on: 9th February 2011