Design automation of embedded systems involves the process of co-designing hardware and software for a given application or, to be more clear, a set of functional and performance. In the aspect of reducing specialized hardware and software co-design for a particular CPU, the most recent grand challenge is developing Computer-Aided Design (CAD) tool support for automatic synthesis of processors. So in this way the problem could be formulated as taking some legacy software code for some and synthesizing a new CPU (its micro-architecture, circuits and even instruction sets) optimal for the given requirements. There are some original theoretical ideas and models such as Conditional Partial Order Graphs (CPOG). CPOG-based methodology has already shown its high potential to solve such problems on simplified example processor. Now research is continuing on more representative, therefore more complex CPU and also well-known one (Core of MCS 80C51). Till now there were several things on this problem done: 1. Code analysing and overlaying all instructions into a CPOG description; 2. Boolean encoding of synthesized CPOG and mapping them to Boolean equation; 3. Translate into HDLs; 4. Synthesis of schematic implementation.
published on: 11th November 2009