- Project Dates: From September 2005 to August 2010
- Project Leader: Dr. Victor Khomenko
- Sponsors: RAEng/EPSRC
The proposed research centres on synthesis and verification of asynchronous (self-timed) circuits. It is argued that asynchrony is important for future development of methods for large-scale design, and thus new synthesis and verification techniques have to be developed. They will be aimed at combating the state space explosion problem, which is the main obstacle for efficient and robust design. This problem reflects the fact that even a relatively small system specification can (and often does) yield a very large state space, requiring memory and computational power for its management beyond the effective capability of available computers. In particular, the verification of both a circuit's data and control paths will be addressed. Relevant tools will be developed and integrated into existing asynchronous design flows.