- Project Dates: From January 2000 to December 2002
- Project Leader: Prof. Alex Yakovlev
- Staff: Prof. DJ Kinniment, Dr. Albert Koelmans, Prof. Maciej Koutny
- Sponsors: EPSRC
The project addresses the development of theoretical models and an associated set of algorithms and software tools for graphical representation and visualisation of highly complex asynchronous circuit behaviour. New tools will enable skilled designers to achieve greater quality and productivity, and greater confidence in their designs. For inexperienced designers, the tools will provide help, through adequate visual association, in understanding the complex character of concurrent processes in asynchronous circuits, and in capturing the various characteristic properties important for their synthesis. These tools will represent this behaviour, often measured in hundreds of thousands of reachable states in an appropriate, intuitively simple, form. These tools will be integrated with the existing software (e.g. Petrify ) for asynchronous circuit synthesis and analysis, experiments showing their effect on the productivity and quality of the design process will be performed. Such as delays and metastability, on the functionality of ACMs. The results of this work will benefit the designers of asynchronous circuits in industrial and academic environments, in particular designers of high-quality and long-life asynchronous circuits, such as control logic for new microcontroller and processor architectures, logic for on-chip interfaces (e.g. between IP cores) and bus controllers; these circuits can be used in low power and portable equipment such as pagers, smartcards, portable sensors and i-buttons. They will also be useful for designers of concurrent systems in general (e.g., embedded, real-time and reactive systems, distributed systems), seeking methods to avoid global synchronisation. With the growth of industrial interest in exploiting benefits of asynchronism in such systems, both in the UK and internationally, this project will create a methodological and experimental basis for design and implementation of systems based on fully or partially asynchronous operation. The software produced in this project will add crucial graphical and visualisation support to the computerised education tools. The latter is essential for training a new generation of logic designers capable of designing asynchronous chips, which requires good understanding of concurrent behaviour in hardware. This project will interact and exploit the results of three EPSRC-funded projects: ASAP (on automated synthesis of asynchronous controllers), HADES (on hazard-free arbiter design) and COMFORT (on asynchronous communication mechanisms for real-time systems design).