- Project Dates: From August 2009 to July 2012
- Project Leader: Dr. Victor Khomenko
- Staff: Prof. Maciej Koutny, Prof. Alex Yakovlev, Mr. Andrey Mokhov, Mr. Ivan Poliakov, Mr. Dominic Wist
- Sponsors: EPSRC
- Partners: University of Manchester
This project redefines conventional asynchronous VLSI tool flows, by incorporating verification into the heart of the design process. Assertion-based verification is used to drive the synthesis procedure by analysing the behaviour of circuits to prove properties which may be exploited for optimisation. Using verification as part of the synthesis procedure represents a major paradigm shift from existing approaches where the validity of optimisations is determined statically and verification is performed after synthesis. Combining synthesis and verification will provide practical and theoretical advances in both areas extending beyond the focus of the project domain.