Author(s): Starodoubstev NA, Yakovlev A, Petrov SY
Abstract: The paper describes the idea of VHDL-based synthesis of asynchronous control circuits from Signal Transition Graphs. A set of VHDL representation forms is defined which allow the designer: (1) to interact with the synthesis process more closely, using the full range of tools (simulation, visualisation etc.) available in VHDL environments. (2) to transition between the forms smoothly, sometimes using ""mixed"" forms, thus efficiently combining partial logic circuit implementations with event-based descriptions of the surrounding parts.
Keywords: asynchronous circuits, design automation, design representation, interactive synthesis, logic synthesis, software tools, vhdl
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Professor Alex Yakovlev
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