FIFO Buffer with Real-Time Interface (1999)

Author(s): Yakovlev A, Kinniment DJ, Xia F

    Abstract: The design of a FIFO buffer supporting fully asynchronous, non-blocking, read and write operations is presented. The circuit consists of a standard self-timed FIFO surrounded by two special interface blocks, In and Out, which together ensure temporal independence between the reading and writing sides. The design has been compared with a known fully asynchronous communication mechanism and found to offer some advantages.

      • Date: January 1999
      • Series Title: Department of Computing Science Technical Report Series
      • Pages: 13
      • Institution: Department of Computing Science, University of Newcastle upon Tyne
      • Publication type: Report
      • Bibliographic status: Published

      Keywords: asychronous communication mechanisms, fifo buffer, four-slot algorithm, real-time systems, self-timed circuits

      Staff

      Professor Alex Yakovlev
      Professor of Computer System Design