Design, Analysis and Implementation of a Self-Timed Duplex Communication System (2002)

Author(s): Yakovlev A, Furber SB, Krenz R

    Abstract: The design of an asynchronous communication system using partially automated techniques is described in this paper. The protocol is formally specified as a protocol state machine and verified with respect to deadlock-freedom and delay-insensitivity using Petri net based model-checking tools. A protocol controller has been synthesized by direct mapping of the Petri net model derived from the protocol specification. The logic implementation was analysed using the Cadence toolkit. While most of the controller's logic is robust to arbitrary gate delay variations, a number of speed-up strategies based on relative timing have been considered. The results of SPICE simulation show the advantages of the direct mapping method compared to logic synthesis. Overall, the design process suggested here offers a generic way to constructing asynchronous communication systems, for both on-chip and off-chip interconnects.

      • Date: 2002
      • Series Title: Department of Computing Science Technical Report Series
      • Pages: 15
      • Institution: Department of Computing Science, University of Newcastle upon Tyne
      • Publication type: Report
      • Bibliographic status: Published

      Keywords: asynchronous circuits, communications, interconnect, protocols, self-timed circuits, synthesis, verification

      Staff

      Professor Alex Yakovlev
      Professor of Computer System Design