EEE Poster - Giga-scale integration and networks on chip
Description
We are investigating new methods for on-chip communication and networking using asynchronous circuits, variability aware strategies and dynamic programming for distributed systems. We design and send for fabrication demonstrator chips in deep submicron technologies as well as 3D die stacking. One such recent design includes a distributed deadlock detection which outperforms all other known solutions.
Researchers
- Dr Frank Burns
- Dr Albert Koelmans
- Dr Terrence Mak
- Dr Gordon Russell
- Dr Danil Sokolov
- Dr Fei Xia
- Prof Alex Yakovlev
More information
- IEEE Transactions on Networks-on-Chip deadlock detection using an embedded network accepted to be published. Please find the manuscript here [PDF]
- NEGUS Project
