Postgraduate Conference Abstract

Microelectronics

Chester, E Year 1

Development of High-Speed Arithmetic Hardware for DSP and Graphics

The Logarithmic Number System (LNS) offers considerable performance advantages in numerically intensive applications such as DSP and graphics. At the limits, there exist applications which require high accuracy and hence use floating-point real arithmetic, where users desire high execution speeds. Conversely, there are high-speed applications employing integer or fixed-point arithmetic, and users require higher accuracy. The initial stage of my PhD will examine advanced DSP algorithms such as adaptive filtering and control using RLS, Kalman, and sub-space methods and identify areas where computational limits in some way restrict an application, the user, or a whole system (eg mobile communications). These will subsequently be modelled in an LNS and specialised hardware implementations designed to optimise performance in terms of speed and accuracy. A more generalised device will be implemented to handle a variety of applications. Alongside establishing application areas, it is hoped that some theoretical contribution will be made within the LNS theory itself.