ADVANCED OXIDE TECHNOLOGY FOR SILICON DEVICES
Supervisor: Nick Wright
Further reduction of conventional SiO2 gate dielectric thickness in complementary metal-oxide-semiconductor (CMOS) scaling causes significant leakage current and reliability problems. Therefore, high permittivity (high-k) gate dielectric materials with substantially thicker films are employed to achieve equivalent capacitance to the SiO2 gate capacitance for maintaining high drive current and at the same time reducing leakage current. The potential high-k dielectric candidates are Al2O3, Ta2O5, TiO2, HfO2, ZrO2, and the silicates and aluminates of Hf and Zr which have dielectric constants ranging from 10 to 100.
All these dielectrics are reviewed with respect to key issues such as permittivity and barrier height, thermodynamic stability, interface quality, film morphology, and process compatibility. The high-k dielectric films are deposited by physical vapour deposition (PVD), chemical vapour deposition (CVD), and molecular beam epitaxy (MBE). Besides those methods, atomic layer deposition (ALD), a promising method, is introduced.