OR-causality in Low-Latency Asynchronous Circuits
Supervisor: Albert Koelmans, Alex Yakovlev
OR-causality, or weak precedence, is a way to increase performance of asynchronous circuits in on-chip interfacing, computation process control, early evaluation in data-flow structures, error-recovery etc. The difficulties in hazard-free implementation of OR-causality restricted its use to the simplest cases of merging. We advance this subject by introducing slack in the taxonomy of OR-causality, which allows latency reduction to be achieved in the context of highly pipelined operation. Petri net models and circuit structures are proposed for the bounded and "almost" unbounded merge cases. The specifics of data or control token stream merging are studied in a number of examples. Those show the applicability of the new merge constructs to a wide range of functional operators, including arithmetic, Boolean and threshold functions.