Olsen, Sarah H
High Performance Strained Si/SiGe NMOSFETs Using A Novel CMOS Architecture
Supervisor: Anthony O'Neill
Performance enhancements of 2-3x are presented for NMOSFETs fabricated with strained Si channels. A novel layer structure comprising Si/Si0.7Ge0.3 on a Si0.85Ge0.15 virtual substrate (VS) offers uncompromised performance for n- and p-channel devices. A high thermal budget process produces devices having excellent Ion/Ioff, gm and sub-threshold characteristics. The VS does not require CMP and the same performance enhancement is achieved with and without a Ti salicide process.