Speaker: Yu Zhou
12th May 2006 , 1pm , E4, Basement, Merz Court, School of EEC
We introduce a design method of asynchronous circuits based on the concept of partial acknowledgement. The method keeps the interconnections of a synchronous Boolean network but maps its gate elements to certain function modules using dual-rail code. We assure that each input and internal variable is partial acknowledged so that the isochronic assumption is satisfied. Furthermore, we explore the possible distributions of partial acknowledgement towards optimal area and performance of the final implementation.