Speaker: Peter Cheung
14th June 2006 , 3.30pm , Research Beehive, Room 2.20
With the availability of low cost, high gate-count FPGAs, it is now possible to map complex DSP algorithms onto hardware with ease and at a low cost. Traditional synthesis methods require an exact description of the system hardware, usually at RTL level. Synthesis tools are then employed to generate optimised designs which performance exactly as the description. Lossy synthesis is an approach whereby the circuit synthesized is allowed to have errors, hence providing an additional trade-off between area, performance, power and accuracy. To demonstrate the lossy synthesis approach, recent results from two research projects carried out in our research group will be described. The first project is to optimally synthesis any sets of 2D non separable filters using heterogenous FPGAs (i.e. FPGAs that contains lookuptables, multipliers and RAMs). Based on the SVD algorithm, our synthesis method produces hardware mapping that is significantly smaller than existing methods. The second project is about computation using a new number representation known as Dual FiXed-point (DFX), which has the advantage of hardware simplicity of fixed point arithmetic and the improved dynamic range of a floating-point representation. New results on error modeling, circuit complexity and application examples will be presented.