Speaker: Qiang Liu
24th September 2010 , 2pm , The Buttery, Merz Court
To meet design goals, designers of computational hardware must perform multiple optimizations, making it difficult to provide optimized designs quickly. Starting from sequential programs, we present an approach combining data reuse, multi-level MapReduce, and pipelining to automatically find the most power-efficient designs that meet speed and area constraints in the design space on Field-Programmable Gate Arrays (FPGAs). The combined design space exploration is formulated as a Geometric Programming model, leading to globally optimized designs. This combined approach enables trade-offs in power, speed and area: we show 63% reduction in power can be achieved with 27% increase in execution time. Compared to the sequential designs, our approach yields designs with up to 158 times reduction in execution time. Moreover, for a given execution time, our combined approach generates designs using up to 28.6% less power than those produced by the same optimizations applied separately and can also find solutions missed by separating the optimizations.