Computational Heterogeneously Timed Networks (COHERENT)

From July 2001 to June 2004
Project Leader(s): Prof. Alex Yakovlev
Sponsors: EPSRC (GR/R32666)
Partners: MBDA, Kingston University.

COHERENT proposes to construct embedded real-time systems of medium complexity as on-chip systems (SoCs) with heterogeneous timing in order to improve timing and energy efficiency of systems for portable and miniature applications in control, robotics, image processing etc. The proposed concept of a hardware-oriented architecture for such systems, called a real-time network on a chip (RTNoC), will consist of computational units of maximum diversity (this issue lies outside the scope of the project) and communication components from (a finite set) of generic asynchronous communication mechanisms (ACMs), which is the focus of this project. The project will deliver a design methodology for RTNoC together with a parametrised library of ACM IP blocks that will, in the longer term, allow the designer to map an application-oriented specification of the system to its implementation with maximum transparency and minimum loss of time and energy resources. It will bridge the gap between the existing (e.g. MASCOT) ideas of building distributed real-time systems and those of globally asynchronous locally synchronous (GALS) for SoCs by investigating techniques for efficient hardware implementation of the elements of communication and multitasking support in the former, and providing a wide range of asynchrony levels, from fully synchronous to wait-free and maximally non-blocking, for the latter. This will enable the seamless composition of systems with time-driven and data-driven parts.


Dr Graeme Chester
Senior Lecturer

Dr Ian Clark
Computing Officer (SAgE - EEE)

Dr Fei Xia
Senior Research Associate

Professor Alex Yakovlev
Professor of Computer System Design