An investigation of Future Metal and Dielectric Cu Barrier Processes and their Impact on Cu Reliability

From October 2004 to November 2007
Project Leader(s): Prof. Anthony O'Neill
Sponsors: Atmel

1. Novel Cu barrier for Cu interconnect
Deposition of Cu barrier layers such as Ta, TaN, or Ti using physical vapour deposition techniques is currently state of the art for 0.13 um Cu interconnect processes. The extendability of the PVD process to 90nm and beyond is questionable due to the poor step coverage properties and integration with porous low-k materials. This work will seek an alternative barrier deposition approach using chemical vapour deposition (CVD) that is compatible with porous low-k dielectric and extendable to any technology node.
The novel barrier of interest will have near absolute Cu barrier property. This property will allow this work to explore the possibility of replacing the contact high resistivity tungsten with the very conducting Cu.

2. Direct Cu plating on the novel Cu barrier
Similar to the PVD barrier materials, PVD Cu seed is also running out of steam; as the device size is shrinking, feature size may not accommodate Cu seed and still leave enough room for void free Cu electroplating. Apart from being a near absolute Cu barrier, this work will be interested in a novel barrier that is reasonably conductive.
The work will also explore the modification of the traditional Cu electroplating in order to deposit Cu directly on the novel barrier without the Cu seed.

3. Capping
The poor interface between Cu and the insulative Cu barrier (SiN, or SiC) is responsible for most of the early failures in the Cu interconnect reliability. This work will seek a Cu capping layer that will improve this interface and increase the Cu interconnect reliability lifetime.

4. Impact of 1-3 on Cu interconnect reliability and device speed
The work will then study the impact of integrated 1, 2, and 3 on the Cu interconnect reliability and device speed.

5. Impact of 1-3 on the stress based on the designed stress sensor
The work will also study the impact of integrated 1, 2, and 3 on the stress using the already designed stress sensor.


Professor Anthony O'Neill
Siemens Professor of Microelectronics