Combining Partial Orders and Symbolic Traversal for Efficient Verification of Asynchronous Circuits (1995)

Author(s): Semenov A, Yakovlev A

      • Date: 29 August - 1 September 1995
      • Conference Name: IFIP TC10 WG10.5 International Conference on Hardware Description Languages and Their Applications (CHDL)
      • Pages: 567-573
      • Publisher: IEEE Press
      • Publication type: Conference Proceedings (inc. abstract)
      • Bibliographic status: Published

      Professor Alex Yakovlev
      Professor of Computer System Design