On-Chip structures for Timing Measurement and Test (2001)

Author(s): Kinniment DJ, Maevsky OV, Bystrov A, Russell G, Yakovlev A

    Abstract: This paper describes the use of digitally set delay lines in conjunction with MUTEX time comparison circuits, to measure on-chip signal path timing differences to accuracies of better than 10ps. Three methods of time measurement are described. The first, which uses parallel MUTEXs with a tapped delay line, is analogous to a flash A/D converter. The second one is similar to a successive approximation method. Both are fast, and efficient, but the second requires less hardware for a large number of bits. The third technique uses a MUTEX to amplify small time differences to a measurable size. Applications for these techniques include adaptive synchronization and input tests, such as data set-up time conditions that currently require the use of very expensive test hardware. We describe an on-chip method of testing these conditions, using uncorrelated signals whose statistics are known, and accurately selecting the conditions to be tested on-chip.

      • Date: 2001
      • Series Title: Department of Computing Science Technical Report Series
      • Pages: 7
      • Institution: Department of Computing Science, University of Newcastle upon Tyne
      • Publication type: Report
      • Bibliographic status: Published

      Keywords: delay measurement, asynchronous circuits, arbitration


      Professor Alex Yakovlev
      Professor of Computer System Design