Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design (2003)

Author(s): Madalinski A, Bystrov A, Khomenko V, Yakovlev A

    Abstract: Synthesis of asynchronous circuits from signal transition graphs (STGs) involves resolution of state encoding conflicts by means of refining the STG specification. The refinement process is generally done automatically using heuristics. It often produces suboptimal solutions or sometimes fails to solve the problem. Thus manual intervention by the designer may be required. A framework is presented for an interactive refinement process aimed to help the designer. It is based on the visualisation of conflict cores, i.e. sets of transitions causing encoding conflicts, which are represented at the level of finite and complete prefixes of STG unfoldings.

    Notes: Special Issue on Best Papers from DATE'2003

      • Journal: IET Computers & Digital Techniques
      • Volume: 150
      • Issue: 5
      • Pages: 285-293
      • Publisher: IEE
      • Publication type: Article
      • Bibliographic status: Published

      Keywords: encoding conflict visualisation; encoding conflict resolution; asynchronous circuit design; asynchronous circuit synthesis; signal transition graphs; STG; state encoding conflict resolution; heuristics; suboptimal solutions; interactive refinement process


      Dr Alex Bystrov

      Professor Alex Yakovlev
      Professor of Computer System Design