Author(s): I.D. Bates;E.G. Chester;D.J. Kinniment
Abstract: The Codesign Finite State Machine (CFSM) formal model provides a suitable approach for the description of hardware/software systems. The POLIS tool from Berkeley implements the CFSM methodology but currently relies on the textually based Esterel specification language as a high level for the description of individual CFSMs. The designer must then use the Ptolemy simulator to interconnect the CFSM network and perform co-simulation. This paper describes work in progress in developing a system which instead aims to use StatemateTM, a statecraft based tool for seamless specification and co-simulation of the entire CFSM network, whilst using the POLLS tool for `C', VHDL code generation and performance estimation. This technique should give the clear advantages of using a graphical specification language together with a uniform co-simulation framework.
Notes: TY - JOUR U1 - 99094776318 Compilation and indexing terms, Copyright 2004 Elsevier Engineering Information, Inc. U2 - Codesign finite state machines (CFSM) Hardware/software codesign systems Esterel programming language
Keywords: Finite automata Sequential machines Computer hardware description languages C (programming language) Codes (symbols) Computer simulation Computer systems programming Response time (computer systems) Computer architecture
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Dr Graeme Chester
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