Newcastle University

Publication

Optimisation of channel thickness in strained Si/SiGe MOSFETs (2003)

Author(s): Kwa KSK, Chattopadhyay S, Olsen SH, Driscoll LS, O'Neill AG

• : Optimisation of channel thickness in strained Si/SiGe MOSFETs

Abstract: It is demonstrated from experimental I-V and C-V data, and confirmed by computer simulation, that strained Si/SiGe MOSFET performance severely degrades below a channel thickness of 7 nm. MOSFETs with strained Si channels of thickness 5 nm, 7 nm and 9 nm have been fabricated using a conventional high thermal budget process. The performance degradation is attributed to Ge diffusion through the strained Si layer, which causes a build up of gate oxide charge. (9 References).

Notes: Franca J Freitas P Piscataway, NJ, USA. ESSDERC 2003. Proceedings of the 33rd European Solid-State Device Research - ESSDERC '03. Estoril, Portugal. IEEE. EDS. Infineon Technol. ATMEL. Tower Semiconductor Ltd. 16-18 Sept. 2003.

• Short Title: Optimisation of channel thickness in strained Si/SiGe MOSFETs

• Date: 16-18 September 2003
• Conference Name: 33rd European Solid-State Device Research
• Pages: 501-504
• Publisher: IEEE
• Publication type: Conference Proceedings (inc. abstract)
• Bibliographic status: Published

• URL: http://dx.doi.org/10.1109/ESSDERC.2003.1256923
• DOI: 10.1109/ESSDERC.2003.1256923