Hock Soon Low
Postgraduate Research Student
- Email: H.S.Low1@ncl.ac.uk
- Telephone: +44 (0)191 222 8926
Thesis/Project Title
Variation Tolerant Asynchronous FPGA Architecture
Thesis Abstract
The Research focus on asynchronous FPGA architecture design aimed at tolerating the unpredictable delay variations caused by process and environment variations in current and future VLSI technology nodes and also targets low power operations, including modes such as dynamic voltage scaling and variable Vdd, as in applications featuring energy harvesting.
Research Areas of Interest
FPGA Architecture, Low Power Embedded System, Reconfigurable circuit, Distributed control, Wireless Sensor
