Dr Gordon Russell
Guest Member of Staff

  • Telephone: +44 (0) 191 208 7324
  • Fax: +44 (0) 191 208 8180
  • Address: E4.40

Dr.G.Russell BSc., PhD., CEng., MIEE, MIEEE. is retired, however he was an academic on the staff of the School of Electrical,  Electronic & Computer  Engineering at the University of Newcastle upon Tyne since 1979.
During this time, in addition to his normal academic duties, he has been involved in a number research projects, namely,

·  Principal Investigator on an SERC funded Project into VLSI Design Methodologies, valued at £300,000.

·  Manager of the Microelectronics Design and Test Centre, funded by SERC -- £600,000.

·  Project Manager on a collaborative project with industry, funded by the DTI -- £375,000. (overall value of the Project £4.0M).

·  Principal Investigator on the ATHIS Project Funded by the EU to a value of 775.000 euros  ( overall value of the Project approx.€7.0M).

 

Before joining the academic staff at the University he was:

·         CAD Consultant with Compeda Ltd.

·         Research Fellow with Wolfson Microelectronics Institute, University of Edinburgh.

·         Post-Doctoral Research Fellow, Department of Electrical Engineering, University of Edinburgh.

·         Research Fellow, Department of Computer Science, University of Edinburgh.

He was involved as Theme Leader in the EDEC Multi-University TLTP Project developing course material in the subject area of Test and Design for Testability.
He was also the Director of SETNET – a semiconductor test network funded by EPSRC.
He has published a considerable number of technical articles on Testing and Design for Testability and has been involved, as Co-author/ Co-Editor, in 6 books related to testing and other aspects involved with the design of VLSI circuits.

His current research interests are in the area related to the design and test of fault tolerant systems to be used in mission critical applications; the development of EDA tools to analyse the effects of semiconductor process variation on system performance parameters; on-chip parametric testing (time measurement).

 

Previous Membership of Professional Groups:
Member of EPSRC College.

Chairman of PGE3(Microelectronic and Semiconductor Devices) of the IEE.
Elected Member of Electronics Divisional Board of the IEE.
Member of PGE10(Circuits and Systems) of the IEE.
Member of PGC6 (Systems Engineering for Automation) of the IEE
Member of PGA2 (Hardware and System Engineering) of the IEE.
Member of PGJ3 ( Electronics Manufacturing) of the IEE
Chairman of EUREL -Technologies.

 

Invited Lectures:
University of Patras, Greece.
UIMP Seville, Spain.
Technical University of Budapest, Hungary.
University of Malaya, Kuala Lumpur , Malaysia.
Hangyang University, Seoul, S. Korea.
LG (Lucky Goldstar), Seoul, S.Korea.
Hyundai, Seoul, S. Korea
ETRI, Taejon, S. Korea.
Samsung, Seoul, S. Korea.
Malardalens Hogskola, Vasteras , Sweden.
University of Las Palmas, Gran Canaria.
Ngee Ann Polytechnic, Singapore,
Semyzen, Singapore.  

 

PhD/MSc Examiner: -- UK
University of Manchester,
UMIST.
Loughborough
Imperial College.
Hull
Huddersfield
Southampton.

 

Ex UK:
University of Manitoba, Canada.

UNSW, Australia.

 

Projects

Undergraduate Teaching

EEE 3007 -- Design and Test of Digital Systems.

Postgraduate Teaching

EEE 8004 -- System on Chip Test Strategies.