School of Engineering

Staff Profile

Dr Danil Sokolov

Senior Research Associate & Research Fellow


Danil is a member of the µSystems Research Group group and his profile can be viewed on Google Scholar.

Research Interests

My main research interests lie in the area of design automation for the next generation of electronics.

We witness the increasing importance of energy efficiency and adaptability to process variations for the next generations of integrated circuits - according to ITRS these are the major challenges for the future of semiconductor industry. However, the state-of-the-art EDA tools are not capable of addressing these challenges due to the outdated design principles where the circuit size and clock speed are the most valuable resources. Moreover, the characteristic feature of circuit area and timing is that they can be optimised in design-time, while the new requirements for energy efficiency and variability resistance are of fundamentally different nature. Their optimisation cannot be rationally addressed in design-time; instead the systems must be built in such a way, that its components adapt their behaviour to the current operating conditions in run-time.

There is clearly a demand for novel, advanced aspects of design automation, which do not fit the existing design practices. I plan to address these demands at the following fronts:

  • Energy token model - to allow explicit representation of energy resource in the circuit throughout the design flow.
  • Automated synthesis of GALS systems - to partition a system into behaviourally decoupled sub-systems which benefit from delay-insensitive communication discipline.
  • Advanced desynchronisation methods - to convert the legacy IP cores into bundled-data and dual-rail asynchronous circuits which are extremely robust to process variation.
  • Synthesis of adaptable circuits - to enable systems high adaptability to variations in environment conditions and operating mode requirements at all granularity levels: fine-gain level of individual gates, functional level of combinational logic, and architectural level of RTL pipeline.