Publication:

Improved Brent & Kung adder (2004)

Author(s): Russell G; Maanmar AH

    Abstract: This paper describes a modification to the Brent & Kung (M-B&K) adder which not only increases the speed of operation but also reduces the amount of the hardware for its implementation. This modified adder is being incorporated into a 32-bit RISC processor which has a concurrent error detection capability. (3 References).

    Notes: Publisher: WSEAS, Greece.

      • Journal: WSEAS Transactions on Circuits and Systems
      • Volume: 3
      • Issue: 9
      • Pages: 2058-2061
      • Publisher: World Scientific and Engineering Academy and Society
      • Publication type: Article
      • Bibliographic status: Published