Publication:

N-MOSFET performance in single and dual channel strained Si/SiGe CMOS architectures (2003)

Author(s): Olsen SH, O'Neill AG, Chattopadhay S, Driscoll LS, Kwa KSK, Paul DJ, Zhang J

  • : N-MOSFET performance in single and dual channel strained Si/SiGe CMOS architectures

Abstract: The performance of single and dual channel strained Si n-MOSFETs fabricated using CMOS process. A TEM image of the strained Si/gate oxide interface was examined. Capacitance-voltage measurement on MOS capacitor was investigated. The gate oxide interface trap density as a function of band gap energy for MOS capacitor fabricated on the single and dual channel architectures was illustrated. Field effect mobility was investigated as a function of vertical effective field on MOSFETs having 10 mu m gate lengths and 5 mu m gate widths. (6 References).

  • Short Title: N-MOSFET performance in single and dual channel strained Si/SiGe CMOS architectures
  • Date: 10-12 December 2003
  • Conference Name: 2003 International Semiconductor Device Research Symposium (IEEE Cat. No.03EX741). IEEE. 2003
  • Pages: 49-50
  • Publisher: IEEE
  • Publication type: Conference Proceedings (inc. abstract)
  • Bibliographic status: Published
    Staff

    Professor Anthony O'Neill
    Siemens Professor of Microelectronics

    Dr Sarah Olsen
    Senior Lecturer