Newcastle University

Background

Terrence Mak obtained a BEng degree from the Chinese University of Hong Kong (CUHK) in 2003. He then studied at MIT in Neural Engineering and was awarded an MPhil degree in 2005. In the same year, he was awarded the Croucher Foundation Scholarship to study PhD at Imperial College London. He completed his PhD in 2009 in circuit design and analysis for networks-on-chip. In the same year, he was awarded a lectureship at Newcastle University. He is also an appointed lecturer at Institute of Neuroscience, Newcastle Biomedicine in the same University.

Qualifications

Ph.D. (Imperial)

Previous Positions

1. Visiting Scientist, Poon’s Neuroengineering Laboratory, MIT (2004-2005)
2. Research Engineer, VLSI group at Sun Microsystems Laboratories, Menlo Park, California (2008-2009)

Honours and Awards

1. US Navel Research Excellence in Neuroengineering (2005)
2. Croucher Foundation Scholarship (2005-2009)

Languages

English, Mandarin, Cantonese

Research Interests

1. VLSI/FPGA circuits and systems
2. Interconnects and network-on-chips (NoC)
3. Brain-machine-interface (BMI)
4. Cognitive on-chip networks
5. Neuromorphic and bio-inspired intelligent system design

Current Work

1. Real-time neurophysiological signal processing
2. Cognitive on-chip networks
3. Energy harvesting circuits and systems

Postgraduate Supervision

Raa'ed Aldujaily (PhD student)

Nizar Dahir (PhD student)

Reza Ramezani (PhD student)

Bo Yu (PhD student)

Junwen Luo (PhD student)

I am always looking for bright and enthusiastic students to join our research group. If your research interests lie in the area of VLSI/FPGA design, brain-machine-interface and cognitive on-chip networks, I would be very happy to talk to you about the possibility of you pursuing research with us.

Esteem Indicators

Program Committee Member, Conferences: ReConFig 2010, NOC 2011

Workshop organizers: UK Async 2007, ARC 2008

Funding

Royal Society International Travel Grant (Principal Investigator) - "3-Dimensional Dynamic Programming Networks", in collaboration with MIT-Harvard Health Sceince and Technology

EPSRC Knowledge Transfer Account (Principal Investigator) - "Real-Time Neural Signal Processing Using Array Processors".

Internal Start-up Grant (Principal Investigator) - "On-Silicon Real-time Neural Signal Processing".

Undergraduate Teaching

EEE 2006 (Analogue Electronics)

• Mak T, Al-Dujaily R, Zhou K, Lam K, Poon C. Dynamic Programming Networks for Large-Scale 3D Chip Integration. IEEE Circuits and Systems Magazine 2011, 11(3), 51-62.
• Mak T, Poon C. 3-D VLSI Systems Integration. The Computer Journal 2012. In Press.
• Al-Dujaily R, Mak T, Xia F, Yakovlev A, Palesi M. Embedded Transitive Closure Networks for Run-Time Deadlock Detection in Networks-on-Chip. IEEE Transactions on Distributed and Parallel Systems 2012, (epub ahead of print).
• Mak T. Truncation error analysis of MTBF computation for multi-latch synchronizers. Microelectronics Journal 2012, 43(2), 160-163.
• Mak T, Lam K, Ng H, Rachmuth G, Poon C. A CMOS current-mode dynamic programming circuit. IEEE Transactions on Circuits and Systems I: Regular Papers 2010, 57(12), 3112-3123.
• Mak T. Adaptive Routing in Network-on-Chips Using a Dynamic Programming Network. IEEE Transactions on Industrial Electronics 2011, 58(8), 3701-3716.
• Mak T, Sedcole P, Cheung P, Luk W. Wave-pipeliend intra-chip signalling for on-FPGA communications. Integration, the VLSI Journal 2010, 43(2), 188-201.
• Mak T, Sedcole P, Cheung PYK, Luk W. Average interconnection delay estimation for on-FPGA communication links. Electronics Letters 2007, 43(17), 918–920.
• Mak T, Rachmuth G, Lam K-P, Poon C. A Component-Based FPGA Design Framework for Neuronal Ion Channel Dynamics Simulations. IEEE Transactions on Neural Systems and Rehabilitation Engineering 2006, 14(4), 410-418.
• Mak T, Lam K-P. Equivalence-set genes partitioning using an evolutionary-DP approach. IEEE Transactions on NanoBioscience 2005, 4(4), 295-300.
• Yu B, Mak T, Li X, Xia F, Yakovlev A, Sun Y, Poon C. A Reconfigurble Hebbian Eigenfilter for Neurophysiological Spike Train Analysis. In: IEEE International Conference on Field Programmable Logic and Applications.2010,Milano, Italy:IEEE
• Mak T, Cheung P, Luk W, Lam K. A DP-network for optimal dynamic routing in network-on-chip. In: 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis. 2009, Grenoble: ACM Press.
• Mak T, D'Alessandro C, Sedcole P, Cheung P, Yakovlev A, Luk W. Global interconnections in FPGAs: modeling and performance analysis. In: 2008 ACM International Workshop on System Level Interconnect Prediction (SLIP 08). 2008, Newcastle, UK: Association for Computing Machinery.
• Mak T, D'Alessandro C, Sedeole P, Cheung PYK, Yakovlev A, Luk W. Implementation of wave-pipelined interconnects in FPGAs. In: Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008. 2008, Newcastle University, Newcastle-upon-Tyne: IEEE Computer Society.
• Mak T, Sedcole P, Cheung P, Luk W. Interconnection length and delay estimation for communication links in FPGAs. In: 2008 ACM International Workshop on System Level Interconnect Prediction (SLIP 08). 2008, Newcastle, UK: Association for Computing Machinery.
• Mak ST, Lam KP, Ng HS, Rachmuth G, Poon CS. A Current-Mode Analog Circuit for Reinforcement Learning Problems. In: ISCAS. 2007, New Orleans, USA: IEEE.
• Mak ST, Sedcole P, Cheung PYK, Luk W, Lam KP. A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing. In: First International Symposium on Network-on-Chip : NOCS 07. 2007, Princeton, New Jersey, USA: IEEE.
• Mak T, Sedcole P, Cheung P, Luk W. On-FPGA Communication Architectures and Design Factors. In: 16th International Conference on Field Programmable Logic and Applications (FPL 2006). 2006, Madrid, Spain: IEEE.
• Yu B, Mak T, Li X, Xia F, Yakovlev A, Sun Y, Poon C. Real-Time FPGA-Based Multichannel Spike Sorting Using Hebbian Eigenfilters. IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS) 2012, 1(4), 502-515.