School of Engineering

Staff Profile

Dr Jesus Urresti Ibanez

Research Associate

Background

Dr Jesus Urresti Ibanez is a Research Associate in the School of Engineering at Newcastle University.

Area of expertise

  • Power devices
  • SiC
  • Interfaces
  • Process fabrication
  • TCAD simulation

Academic background

  • BSc in Physics, Universitat Autonoma de Barcelona 1999
  • PhD in Electronic Engineering, Universitat Autonoma de Barcelona 2008

Google scholar: Click here.

SCOPUS: Click here.

Research

Jesús is a member of the Emerging Electronic Technologies group.

Publications

  • Arith F, Urresti J, Vasilevskiy K, Olsen S, Wright N, O'Neill A. Increased Mobility in Enhancement Mode 4H-SiC MOSFET Using a Thin SiO2 / Al2O3 Gate Stack. IEEE Electron Device Letters 2018, 39(4), 564-567.
  • Fayyaz A, Romano G, Urresti J, Riccio M, Castellazzi A, Irace A, Wright N. A Comprehensive Study on the Avalanche Breakdown Robustness of Silicon Carbide Power MOSFETs. Energies 2017, 10(4), 452.
  • Roy SK, Ibanez JU, O'Neill AG, Wright NG, Horsfall AB. Characterisation of 4H-SiC MOS capacitor with a protective coating for harsh environments applications. In: 2016 European Conference on Silicon Carbide & Related Materials (ECSCRM). 2017, Halkidiki, Greece: Trans Tech Publications Ltd.
  • Fayyaz A, Castellazzi A, Romano G, Riccio M, Irace A, Urresti J, Wright N. Influence of gate bias on the avalanche ruggedness of SiC power MOSFETs. In: Proceedings of the 29th International Symposium on Power Semiconductor Devices and ICs, ISPSD 2017. 2017, Sapporo, Japan: Institute of Electrical and Electronics Engineers Inc.
  • Castellazzi A, Fayyaz A, Romano G, Riccio M, Irace A, Urresti-Ibanez J, Wright N. Transient out-of-SOA robustness of SiC power MOSFETs. In: 2017 IEEE International Reliability Physics Symposium (IRPS). 2017, California, USA: IEEE.
  • Fayyaz A, Castellazzi A, Romano G, Riccio M, Irace A, Urresti J, Wright N. UIS failure mechanism of SiC power MOSFETs. In: 2016 IEEE 4th Workshop on Wide Bandgap Power Devices and Applications (WiPDA). 2016, Arkansas, USA: IEEE.
  • Urresti J, Hidalgo S, Flores D, Hevia D. 3.3 kV PT-IGBT with voltage-sensor monolithically integrated. IET Circuits, Devices and Systems Series 2014, 8(3), 182-187.
  • Perpina X, Cortes I, Urresti-Ibañez J, Jorda X, Rebollo J. Layout role in failure physics of IGBTs under overloading clamped inductive turnoff. IEEE TRANSACTIONS ON ELECTRON DEVICES 2013, 60(2), 598-605.
  • Perpiñà X, Cortés I, Urresti-Ibañez J, Jordà X, Rebollo J, Millán J. Clamped inductive turn-off failure in high-voltage NPT-IGBTs under overloading conditions. In: 2012 24TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS (ISPSD). 2012, Bruges, BELGIUM: IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA.
  • Cortés I, Perpiñà X, Urresti J, Jordà Xavier, Rebollo J. Study of layout influence on ruggedness of NPT-IGBT devices by physical modelling. MICROELECTRONICS RELIABILITY 2012, 52(9-10), 2471-2476.
  • Perpina Xavier, Serviere J-F, Urresti-Ibañez Jesús, Cortes Ignasi, Jorda Xavier, Hidalgo Salvador, Rebollo Jose, Mermet-Guyennet Michel. Analysis of clamped inductive turnoff failure in railway traction IGBT power modules under overload conditions. Industrial Electronics, IEEE Transactions on 2011, 58(7), 2706-2714.
  • Perpiñà X, Cortés I, Urresti-Ibañez J, Jordà X, Rebollo J, Millán J. Edge termination impact on clamped inductive turn-off failure in high-voltage IGBTs under overcurrent conditions. In: 2011 IEEE 23RD INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS (ISPSD). 2011, San Diego, CA: IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA.
  • Cortés I, Toulon G, Morancho F, Urresti J, Perpiñà X, Villard B. Analysis and optimization of safe-operating-area of LUDMOS transistors based on 0.18 µm SOI CMOS technology. SEMICONDUCTOR SCIENCE AND TECHNOLOGY 2010, 25(4), 045013.
  • Urresti J, Hidalgo S, Flores D, Rebollo J. Lateral punch-through TVS devices: design and fabrication. In: 7th Spanish Conference on Electron Devices. 2009, Univ Santiago de Compostelea, Santiago de Compostela, SPAIN: IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA.
  • Perpiñà X, Serviere JF, Jorda X, Hidalgo S, Urresti-Ibanez J, Rebollo J, Mermet-Guyennet M. Over-current turn-off failure in high voltage IGBT modules under clamped inductive load. In: EPE: 2009 13TH EUROPEAN CONFERENCE ON POWER ELECTRONICS AND APPLICATIONS. 2009, Barcelona, SPAIN: IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA.
  • Perpiñà X, Serviere J, Jordà X, Fauquet A, Hidalgo S, Urresti-Ibañez J, Rebollo J, Mermet-Guyennet M. IGBT module failure analysis in railway applications. MICROELECTRONICS RELIABILITY 2008, 48(8-9), 1427-1431.
  • Castellazzi A, Ciappa M, Fichtner W, Urresti-Ibañez J, Mermet-Guyennet M. Integrated Compact Modelling of a Planar-Gate Non-Punch-Through 3.3 kV-1200A IGBT Module for Insightful Analysis and Realistic Interpretation of the Failure Mechanisms. In: 19th International Symposium on Power Semiconductor Devices and ICs. 2007, Cheju Isl, SOUTH KOREA: IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA.
  • Urresti-Ibañez J, Castellazzi A, Piton M, Rebollo J, Mermet-Guyennet M, Ciappa M. Robustness test and failure analysis of IGBT modules during turn-off. MICROELECTRONICS RELIABILITY 2007, 47(9-11), 1725-1729.
  • Cortés I, Roig J, Flores D, Urresti J, Hidalgo S, Rebollo J. A numerical study of field plate configurations in RF SOI LDMOS transistors. SOLID-STATE ELECTRONICS 2006, 50(2), 155-163.
  • Roig J, Flores D, Cortes I, Urresti J, Hidalgo S, Rebollo J, Richter S. Non-uniform temperature and heat generation in thin-film SOI LDMOS with uniform drift doping. In: 7th International Seminar on Power Semiconductors (ISPS 04). 2006, Prague, CZECH REPUBLIC: IEE-INST ELEC ENG, MICHAEL FARADAY HOUSE SIX HILLS WAY STEVENAGE, HERTFORD SG1 2AY, ENGLAND.
  • Roig J, Flores D, Urresti J, Cortes I, Hidalgo S, Millan J. A physically based thermal model for high‐voltage thin‐film SOI LDMOS in short circuit operation. PHYSICA STATUS SOLIDI A-APPLICATIONS AND MATERIALS SCIENCE 2005, 202(9), 1862-1868.
  • Urresti J, Hidalgo S, Flores D, Roig J, Rebollo J, Mazarredo I. A quasi-analytical breakdown voltage model in four-layer punch-through TVS devices. SOLID-STATE ELECTRONICS 2005, 49(8), 1309-1313.
  • Cortés I, Roig J, Flores D, Urresti J, Hidalgo Salvador, Rebollo J. Analysis of hot-carrier degradation in a SOI LDMOS transistor with a steep retrograde drift doping profile. MICROELECTRONICS RELIABILITY 2005, 45(3-4), 493-498.
  • Cortes I, Roig J, Flores D, Urresti J, Hidalgo S, Millan J. Degradation analysis in SOI LDMOS transistors with steep retrograde doping profile and source field plate. In: 5th Spanish Conference on Electron Devices. 2005, Tarragona, SPAIN: IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA.
  • Roig J, Flores D, Urresti J, Hidalgo S, Rebollo J. Heat Generation Analysis in SOI LDMOS Power Transistors. In: NATO Advanced Research Workshop on Science and Technology of Semiconductor-on-Insulator Structures and Devices Operating in a Harsh Environment. 2005, Kiev, UKRAINE: SPRINGER, PO BOX 17, 3300 AA DORDRECHT, NETHERLANDS.
  • Urresti J, Hidalgo Salvador, Flores D, Roig J, Cortés I, Rebollo J. Lateral punch-through TVS devices for on-chip protection in low-voltage applications. MICROELECTRONICS RELIABILITY 2005, 45(7-8), 1181-1186.
  • Roig J, Flores D, Urresti J, Hidalgo S, Rebollo J. Modeling of non-uniform heat generation in LDMOS transistors. SOLID-STATE ELECTRONICS 2005, 49(1), 77-84.
  • Roig J, Flores D, Jordà X, Urresti J, Vellvehi M, Rebollo J, Milan J. An analytical model to predict the short-circuit thermal failure in SOI LDMOS with Linear Doping Profile. In: 24th International Conference on Microelectronics (MIEL 2004). 2004, Nis, SERBIA: IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA.
  • Roig J, Urresti J, Cortes I, Flores D, Hidalgo S, Millan J. Efficiency of SOI-like structures for reducing the thermal resistance in thin-film SOI power LDMOSFETs. IEEE ELECTRON DEVICE LETTERS 2004, 25(11), 743-745.
  • Urresti J, Hidalgo S, Flores D, Roig J, Vellvehi M, Rebollo J. Modellization of the breakdown voltage of four-layer punch-through TVS diodes. In: 24th International Conference on Microelectronics (MIEL 2004). 2004, Nis, SERBIA: IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA.
  • Urresti J, Hidalgo Salvador, Flores D, Roig J, Rebollo J, Mazarredo I. Optimisation of very low voltage TVS protection devices. MICROELECTRONICS JOURNAL 2003, 34(9), 809-813.
  • Urresti J, Hidalgo S, Flores D, Roig J, Rebollo J, Millan J. Low voltage TVS devices: Design and fabrication. In: 25th International Semiconductor Conference. 2002, SINAIA, ROMANIA: IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA.