Undergraduate

modules

Modules

EEE3012 : Integrated Circuit Design

Semesters
Semester 2 Credit Value: 10
ECTS Credits: 5.0

Aims

To introduce the students to the fundamentals of VLSI design and provide them with the essential knowledge about the main themes, so that, in future, the students will be able to readily apply this knowledge in industry or research or further enhance it by self study.

Outline Of Syllabus

Transistor topology; transistor equations; CMOS process steps; fabrication; yield; design rules for custom layout. Complex gates; pseudo NMOS; dynamic logic; dynamic cascaded logic; domino logic; 2 and 4 phase logic; pass transistor logic. Contorl and timing; synchronous and asychronous; self-timed systems; multi-phase clocks; register to register transfer; examples of ALU, shifters, and registers. Layout, hand layout, graphical layout, low-level language; design rule checking; stick diagrams; placement of cells; simulation of design; function generation from masks; test pattern generation; high-level languages; structured design methodology for VLSI; hierarchical design techniques and examples.

Serial addition; bit-serial multipliers; systolic arrays; analogue voltage dividers; current mirrors; differential amplifiers; wide range amplifiers. Effects of scaling circuit dimensions; physical limits to device fabrication. Optional extended course work for final year students, using VLSI design software to produce a chip to meet a given specification; the chip may be fabricated if the design is successful.

Case Study Lecture

Design of a MSI chip using proprietary CAD system; use of circuit description language; layout considerations.

Teaching Methods

Teaching Activities
Category Activity Number Length Student Hours Comment
Guided Independent StudyAssessment preparation and completion240:3012:00Revision for final exam
Guided Independent StudyAssessment preparation and completion12:002:00Final exam
Scheduled Learning And Teaching ActivitiesLecture241:0024:00N/A
Guided Independent StudyIndependent study162:0062:00Reviewing lecture notes; general reading
Total100:00
Jointly Taught With
Code Title
EEE8020Advanced VLSI Design
Teaching Rationale And Relationship

Lectures provide core material and guidance for further reading, problem solving practice is intergrated into lecture structure.

Assessment Methods

The format of resits will be determined by the Board of Examiners

Exams
Description Length Semester When Set Percentage Comment
Written Examination1202A100N/A
Exam Pairings
Module Code Module Title Semester Comment
2N/A
Assessment Rationale And Relationship

The examination provides the opportunity for the student to demonstrate their understanding of the course material. The problem solving aspects of the assessment enable the student to demonstrate that they are able to apply this understanding and their analysis and synthesis skills to novel situations.

Reading Lists

Timetable