Module Catalogue 2016/17

EEE8004 : System-on-Chip Test Strategies

  • Offered for Year: 2016/17
  • Module Leader(s): Dr Gordon Russell
  • Owning School: Electrical & Electronic Engineering
  • Teaching Location: Newcastle City Campus
Semesters
Semester 1 Credit Value: 15
ECTS Credits: 8.0
Pre Requisites
Pre Requisite Comment

or equivalent if UG degree not taken at Newcastle.

Co Requisites
Co Requisite Comment

N/A

Aims

This module gives the student an understanding of design for test methodologies and to introduce them to the VHDL Language and the design tools based on VHDL. The course covers the following topics: techniques for ATPG, Fault Simulation and Testability Analysis for VLSI circuits; methodologies for designing testable circuits; VHDL Language and design tools based on the VHDL Language.

Outline Of Syllabus

Introduction:
Importance of test; why electronic systems malfunction/fail; difficulty of testing VLSI circuits and systems.

Test Engineers Tool Kit:
Automatic test pattern generation: what it is, the basic issues related to test pattern generation, a description of the path sensitation method and examples of its use.
Fault simulation: what it is, the fault simulation process, a description of fault simulations methods (Parallel and Concurrent) and examples of their use.
Testability Analysis: what it is, testability measurement parameters, a description of a testability analyser and examples of it use.

Design for Testability(DFT):
What is design for testability; the impact of the incorporation of DFT into a design; structured approach to DFT; objectives of Built in Self Test (BIST); essential components of a BIST system and its problematic issues; example of a BIST scheme.

Hardware Description Languages:
Introduction to VHDL, behavioural modelling of the commonly used functional blocks in a digital design and simulation in a VHDL environment; design of a test benches.

Advanced Material drawn from:
Fault tolerant design techniques; testing embedded memories, testing System on Chip, testing analogue circuits, Boundary Scan,on-chip time measurement techniques, challenges of testing billion transistor chips.

Learning Outcomes

Intended Knowledge Outcomes

To attain both factual and conceptual knowledge associated with:
The techniques for ATPG, Fault and Testability Analysis for VLSI circuits.
The methodologies for designing testable circuits.
The VHDL Language
The design tools based on the VHDL Language.

Intended Skill Outcomes

Ability to perform test pattern generation and fault simulation on VLSI circuits. Design complex circuits using VHDL and incorporate BIST into the design.

Graduate Skills Framework

Graduate Skills Framework Applicable: Yes
  • Cognitive/Intellectual Skills
    • Critical Thinking : Present
    • Data Synthesis : Assessed
    • Numeracy : Assessed
    • Information Literacy
      • Use Of Computer Applications : Present
  • Self Management
    • Personal Enterprise
      • Initiative : Assessed
      • Problem Solving : Assessed
    • Budgeting : Assessed
  • Application
    • Commercial Acumen
      • Market Awareness : Present
      • Financial Awareness : Present

Teaching Methods

Teaching Activities
Category Activity Number Length Student Hours Comment
Scheduled Learning And Teaching ActivitiesLecture361:0036:00N/A
Guided Independent StudyAssessment preparation and completion360:3018:00Revision for final exam
Guided Independent StudyAssessment preparation and completion13:003:00Final exam
Scheduled Learning And Teaching ActivitiesPractical51:005:00VHDL
Guided Independent StudyIndependent study158:0058:00Review Recap lectures; tutorial problems; understanding of concepts/principles outlined in lectures
Guided Independent StudyIndependent study122:3030:00Independent study of advanced material.
Total150:00
Jointly Taught With
Code Title
EEE3007Design and Test of Digital Systems
Teaching Rationale And Relationship

Lectures provide the core material and guidance for further reading and subsequent advancement of knowledge about the design and test of VLSI circuits and systems.

Reading Lists

Assessment Methods

The format of resits will be determined by the Board of Examiners

Exams
Description Length Semester When Set Percentage Comment
Written Examination1801A100N/A
Exam Pairings
Module Code Module Title Semester Comment
EEE3007Design and Test of Digital Systems1N/A
Assessment Rationale And Relationship

The closed book examination allows the students to demonstrate their problem solving skills together with their knowledge and understanding of the subject matter in the lectures.

Timetable

Past Exam Papers

General Notes

Original Handbook text:

Disclaimer: The information contained within the Module Catalogue relates to the 2016/17 academic year. In accordance with University Terms and Conditions, the University makes all reasonable efforts to deliver the modules as described. Modules may be amended on an annual basis to take account of changing staff expertise, developments in the discipline, the requirements of external bodies and partners, and student feedback. Module information for the 2017/18 entry will be published here in early-April 2017. Queries about information in the Module Catalogue should in the first instance be addressed to your School Office.