|Semester 1 Credit Value:||15|
or equivalent if UG degree not taken at Newcastle.
This module gives the student an understanding of design for test methodologies and to introduce them to the VHDL Language and the design tools based on VHDL. The course covers the following topics: techniques for ATPG, Fault Simulation and Testability Analysis for VLSI circuits; methodologies for designing testable circuits; VHDL Language and design tools based on the VHDL Language.
Importance of test; why electronic systems malfunction/fail; difficulty of testing VLSI circuits and systems.
Test Engineers Tool Kit:
Automatic test pattern generation: what it is, the basic issues related to test pattern generation, a description of the path sensitation method and examples of its use.
Fault simulation: what it is, the fault simulation process, a description of fault simulations methods (Parallel and Concurrent) and examples of their use.
Testability Analysis: what it is, testability measurement parameters, a description of a testability analyser and examples of it use.
Design for Testability(DFT):
What is design for testability; the impact of the incorporation of DFT into a design; structured approach to DFT; objectives of Built in Self Test (BIST); essential components of a BIST system and its problematic issues; example of a BIST scheme.
Hardware Description Languages:
Introduction to VHDL, behavioural modelling of the commonly used functional blocks in a digital design and simulation in a VHDL environment; design of a test benches.
Advanced Material drawn from:
Fault tolerant design techniques; testing embedded memories, testing System on Chip, testing analogue circuits, Boundary Scan,on-chip time measurement techniques, challenges of testing billion transistor chips.
To attain both factual and conceptual knowledge associated with:
The techniques for ATPG, Fault and Testability Analysis for VLSI circuits.
The methodologies for designing testable circuits.
The VHDL Language
The design tools based on the VHDL Language.
Ability to perform test pattern generation and fault simulation on VLSI circuits. Design complex circuits using VHDL and incorporate BIST into the design.
|Graduate Skills Framework Applicable:||Yes|
|Scheduled Learning And Teaching Activities||Lecture||36||1:00||36:00||N/A|
|Guided Independent Study||Assessment preparation and completion||36||0:30||18:00||Revision for final exam|
|Guided Independent Study||Assessment preparation and completion||1||3:00||3:00||Final exam|
|Scheduled Learning And Teaching Activities||Practical||5||1:00||5:00||VHDL|
|Guided Independent Study||Independent study||1||58:00||58:00||Review Recap lectures; tutorial problems; understanding of concepts/principles outlined in lectures|
|Guided Independent Study||Independent study||12||2:30||30:00||Independent study of advanced material.|
|EEE3007||Design and Test of Digital Systems|
Lectures provide the core material and guidance for further reading and subsequent advancement of knowledge about the design and test of VLSI circuits and systems.
The format of resits will be determined by the Board of Examiners
|Module Code||Module Title||Semester||Comment|
|EEE3007||Design and Test of Digital Systems||1||N/A|
The closed book examination allows the students to demonstrate their problem solving skills together with their knowledge and understanding of the subject matter in the lectures.
Original Handbook text:
Disclaimer: The information contained within the Module Catalogue relates to the 2016/17 academic year. In accordance with University Terms and Conditions, the University makes all reasonable efforts to deliver the modules as described. Modules may be amended on an annual basis to take account of changing staff expertise, developments in the discipline, the requirements of external bodies and partners, and student feedback. Module information for the 2017/18 entry will be published here in early-April 2017. Queries about information in the Module Catalogue should in the first instance be addressed to your School Office.