|Semester 1 Credit Value:||15|
or equivalent if UG degree not taken at Newcastle.
This module gives the student an understanding of design for test methodologies and to introduce them to the VHDL Language and the design tools based on VHDL. The course covers the following topics: techniques for ATPG, Fault Simulation and Testability Analysis for VLSI circuits; methodologies for designing testable circuits; VHDL Language and design tools based on the VHDL Language.
Introduction to the design of electronic systems
What are the problems - specification, testability, modelling, verification.
Automatic Test Pattern Generation Techniques
Importance of test, difficulty of testing VLSI circuits and systems, structural test pattern generation methods.
Design for Testability
What is design for testability; basic approaches - ad hoc and structured. Built in Self Test (BIST), self-checked systems; testability analysis
What is a stimulator, levels of stimulation, applications: verification and fault simulation.
Hardware Description Languages
Introduction to VHDL, behavioural modelling and simulation in a VHDL environment; user interfaces and test benches.
Advanced Material drawn from:
Using commercial CAD tools for VLSI design - the design of a small system will be undertaken; fault tolerant design techniques; testing mixed analogue / digital circuits, testing MCMs, Boundary Scan, Iddq testing.
To attain both factual and conceptual knowledge associated with:
The techniques for ATPG, Fault and Testability Analysis for VLSI circuits.
The methodologies for designing testable circuits.
The VHDL Language
The design tools based on the VHDL Language.
Ability to perform test pattern generation and fault simulation on VLSI circuits. Design complex circuits using VHDL and incorporate BIST into the design.
|Graduate Skills Framework Applicable:||Yes|
|Guided Independent Study||Assessment preparation and completion||36||0:30||18:00||Revision for final exam|
|Guided Independent Study||Assessment preparation and completion||1||3:00||3:00||Final exam|
|Scheduled Learning And Teaching Activities||Lecture||36||1:00||36:00||N/A|
|Scheduled Learning And Teaching Activities||Practical||5||1:00||5:00||VHDL|
|Guided Independent Study||Independent study||12||2:30||30:00||Independent study of advanced material.|
|Guided Independent Study||Independent study||1||58:00||58:00||Review Recap lectures; tutorial problems; understanding of concepts/principles outlined in lectures|
|EEE3007||Design and Test of Digital Systems|
Lectures provide the core material and guidance for further reading and subsequent advancement of knowledge about the design and test of VLSI circuits and systems.
The format of resits will be determined by the Board of Examiners
|Module Code||Module Title||Semester||Comment|
|EEE3007||Design and Test of Digital Systems||1||N/A|
The closed book examination allows the students to demonstrate their problem solving skills together with their knowledge and understanding of the subject matter in the lectures.
Original Handbook text:
Note: The Module Catalogue now reflects module information relating to academic year 16/17. Please contact your School Office if you require module information for a previous academic year.
Disclaimer: The University will use all reasonable endeavours to deliver modules in accordance with the descriptions set out in this catalogue. Every effort has been made to ensure the accuracy of the information, however, the University reserves the right to introduce changes to the information given including the addition, withdrawal or restructuring of modules if it considers such action to be necessary.