Module Catalogue 2018/19

EEE8100 : Software tools for Digital System Design

  • Offered for Year: 2018/19
  • Module Leader(s): Dr Alex Bystrov
  • Owning School: Engineering
  • Teaching Location: Newcastle City Campus
Semesters
Semester 2 Credit Value: 10
ECTS Credits: 5.0
Pre Requisites
Code Title
EEE3007Design and Test of Digital Systems
Pre Requisite Comment

N/A

Co Requisites
Co Requisite Comment

N/A

Aims

To outline the CAD tools and the VLSI design flow in the context of International Technology Roadmap on Semiconductors.
To study design capture, simulation and design synthesis techniques. To understand the characteristics of the algorithms, and hence the strengths and weaknesses of the tools.
To familiarise and to develop skills in operating the industry standard CAD tool.

Outline Of Syllabus

1. The following objectives are attained in about 16 formal lectures
- An overview of existing CAD tools and their evolution projected into the near future according to the International Technology Roadmap on Semiconductors.
- Concurrency: modelling verification and interface protocol capture as a Signal Transition Graph.
- Design capture by using Verilog and VHDL languages. Three levels of system description. Logic synthesis.
- Compact representation of state sets as Binary Decision Diagrams.
- Scheduling of operations and Data Flow Graphs.

2. Problem solving skills are exercised in the tutorials/seminars.

3. The coursework includes familiarisation exercises and a mini-project, within which a student develops a case study by analogy to the offered examples. The coursework develops skills on operating the industry standard CAD tools, on various methods of design capture (schematic, Verilog and VHDL), simulation and debugging.

Learning Outcomes

Intended Knowledge Outcomes

An understanding of what CAD tools are available for digital design and where they are used.
An understanding of different design capture methods and the tools that support them.
Petri Nets and asynchronous design.
A knowledge of synthesis algorithms, and the underlying strengths and weaknesses of the tools.
The use of Verilog and VHDL languages in design capture and netlists.
The use of BDDs for representation of large state spaces.
Scheduling of operations and Data flow graphs.

Intended Skill Outcomes

Ability to use the design environment.
Ability to use synthesis tools and to produce an efficient design.
Good design practices.

Graduate Skills Framework

Graduate Skills Framework Applicable: Yes
  • Cognitive/Intellectual Skills
    • Critical Thinking : Present
    • Data Synthesis : Assessed
    • Numeracy : Assessed
    • Literacy : Assessed
    • Information Literacy
      • Synthesise And Present Materials : Assessed
      • Use Of Computer Applications : Assessed
  • Self Management
    • Planning and Organisation
      • Goal Setting And Action Planning : Assessed
      • Decision Making : Assessed
    • Personal Enterprise
      • Initiative : Assessed
      • Problem Solving : Assessed
  • Interaction
    • Communication
      • Written Other : Assessed

Teaching Methods

Teaching Activities
Category Activity Number Length Student Hours Comment
Scheduled Learning And Teaching ActivitiesLecture22:004:00N/A
Guided Independent StudyAssessment preparation and completion115:0015:00Report
Guided Independent StudyAssessment preparation and completion240:3012:00Revision for final exam
Guided Independent StudyAssessment preparation and completion11:001:00Final exam
Scheduled Learning And Teaching ActivitiesPractical115:0015:00Supervised Practical (coursework)
Scheduled Learning And Teaching ActivitiesPractical13:003:00Hands on tutorial
Guided Independent StudyDirected research and reading132:0026:00General reading in support of lectures and practicals.
Guided Independent StudyProject work124:0024:00Design and performance of experiments.
Total100:00
Teaching Rationale And Relationship

Lectures provide core material and guidance for further reading, problem solving is integrated into lecture structure and computer based learning. The study of the International Technology Roadmap on Semiconductors provides the philosophical understanding of demands of the modern semiconductor design industry.

Practicals develop the skills in using the industry standard tools, which is of direct relevance to employability of graduates.

The mini-project enforces the active learning approach, exercises design skills and faciliitates efficient knowledge/skill transfer through continuous assessment.

Reading Lists

Assessment Methods

The format of resits will be determined by the Board of Examiners

Other Assessment
Description Semester When Set Percentage Comment
Report2M751500 words excluding the illustrations and appendices, the source code must be attached.
Prof skill assessmnt2M25Presentation
Assessment Rationale And Relationship

The examination provides the opportunity for students to demonstrate their understanding of the course material. The problem solving aspects of the assessment enable students to demonstrate that they are able to apply this understanding and their analysis and synthesis skills to novel situations.

The assessed report represents the part of the objectives which require the use of the software tools. It also tests the ability to combine various problem-specific parts of knowledge and skills into a complete design experience. It is impossible to design engineering objects without error. The project-type assessment exposes the ability of a student to discover and correct such errors.

Timetable

Past Exam Papers

General Notes

Original Handbook text:

Disclaimer: The information contained within the Module Catalogue relates to the 2018/19 academic year. In accordance with University Terms and Conditions, the University makes all reasonable efforts to deliver the modules as described. Modules may be amended on an annual basis to take account of changing staff expertise, developments in the discipline, the requirements of external bodies and partners, and student feedback. Module information for the 2018/19 entry will be published here in early-April 2018. Queries about information in the Module Catalogue should in the first instance be addressed to your School Office.