Victor obtained MSc with distinction in Computer Science, Applied Mathematics and Teaching of Mathematics and Computer Science in 1998 from Kiev Taras Shevchenko University, and PhD in Computing Science in 2003 from Newcastle University.
In January 2005 Victor became a Lecturer in this School, and then in September 2005 he obtained a Royal Academy of Engineering / EPSRC Post-doctoral Research Fellowship and worked on the DAVAC project. After the end of this award, in September 2010, he switched back to Lectureship.
My research is concentrated on the theory of distributed and concurrent systems, in particular on application of formal techniques to verification and synthesis of such systems. From September, 1999, I have been working on model checking of Petri nets and synthesis of asynchronous (self-timed) circuits using Petri net unfoldings.
Currently I work on the Verification-Driven Asynchronous Design (VERDAD) project.
5-years research fellowship from Royal Academy of Engineering and EPSRC.
Best paper award at ACSD'04 conference, and best paper selection at DATE'03, ACSD'03, ACSD'04, ACSD'06, ACSD'07, Petri Nets'08, ACSD'09 and CONCUR'12 conferences.
Invited speaker at UK Asynchronous Forum'06 and International Workshop on Petri nets and Software Engineering (PNSE'11).
Organised Workshop on UnFOlding and partial order techniques (UFO'07), First International Workshop on BALSA Re-Synthesis (RESYN'09), and the Advanced Tutorial on Theory and Applications of Petri Net Unfoldings at Petri Nets 2012 conference.
I am the PI on the EPSRC-funded Verification-Driven Asynchronous Design (VERDAD) project.
Currently I am a module leader for the following modules:
CSC1025: Foundation Mathematics for Computing Science
CSC2014: Modelling and Computation
CSC8099: MSc Project and Dissertation
I am also the Degree Programme Directors and Admissions Officer for the MSc Computer Science degree, and a member of the PhD Progress Committee and the School Learning, Teaching and Student Experience Committee.