EEE3007 : Design and Test of Digital Systems
- Offered for Year: 2019/20
- Module Leader(s): Dr Gordon Russell
- Owning School: Engineering
- Teaching Location: Newcastle City Campus
Semesters
| Semester 1 Credit Value: | 10 |
| ECTS Credits: | 5.0 |
Aims
This module gives the student an understanding of design for test methodologies and to introduce them to the VHDL Language and the design tools based on VHDL. The course covers the following topics: techniques for ATPG, Fault Simulation and Testability Analysis for VLSI circuits; methodologies for designing testable circuits; VHDL Language and design tools based on the VHDL Language.
Outline Of Syllabus
Introduction:
Importance of test; why electronic systems malfunction/fail; difficulty of testing VLSI circuits and systems.
Test Engineers Tool Kit:
Automatic test pattern generation: what it is, the basic issues related to test pattern generation, a description of the path sensitation method and examples of its use.
Fault simulation: what it is, the fault simulation process, a description of fault simulations methods (Parallel and Concurrent) and examples of their use.
Testability Analysis: what it is, testability measurement parameters, a description of a testability analyser and examples of it use.
Design for Testability(DFT):
What is design for testability; the impact of the incorporation of DFT into a design; structured approach to DFT; objectives of Built in Self Test (BIST); essential components of a BIST system and its problematic issues; example of a BIST scheme.
Hardware Description Languages:
Introduction to VHDL, behavioural modelling of the commonly used functional blocks in a digital design and simulation in a VHDL environment; design of a test bench.
Teaching Methods
Teaching Activities
| Category | Activity | Number | Length | Student Hours | Comment |
|---|---|---|---|---|---|
| Guided Independent Study | Assessment preparation and completion | 24 | 0:30 | 12:00 | Revision for final exam |
| Guided Independent Study | Assessment preparation and completion | 1 | 2:00 | 2:00 | Final exam |
| Scheduled Learning And Teaching Activities | Lecture | 24 | 1:00 | 24:00 | N/A |
| Scheduled Learning And Teaching Activities | Practical | 5 | 1:00 | 5:00 | VHDL |
| Guided Independent Study | Independent study | 1 | 57:00 | 57:00 | Review Recap lectures; solve tutorial problems; understand concepts/principles outlined in lectures |
| Total | 100:00 |
Jointly Taught With
| Code | Title |
|---|---|
| EEE8122 | System on Chip Test and Validation |
Teaching Rationale And Relationship
Lectures provide the core material and guidance for further reading and subsequent advancement of knowledge about the design and test of VLSI circuits and systems.
Assessment Methods
The format of resits will be determined by the Board of Examiners
Exams
| Description | Length | Semester | When Set | Percentage | Comment |
|---|---|---|---|---|---|
| Written Examination | 120 | 1 | A | 100 | N/A |
Exam Pairings
| Module Code | Module Title | Semester | Comment |
|---|---|---|---|
| EEE8122 | System on Chip Test and Validation | 1 | N/A |
Assessment Rationale And Relationship
The closed book examination allows the students to demonstrate their problem solving skills together with their closed knowledge and understanding of the subject matter outlined in the lectures.
Semester 1 Study Abroad students will be able to sit the assessment earlier.
Reading Lists
Timetable
- Timetable Website: www.ncl.ac.uk/timetable/
- EEE3007's Timetable