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Module

EEE3007 : Design and Test of Digital Systems (Inactive)

  • Inactive for Year: 2021/22
  • Module Leader(s): Dr Gordon Russell
  • Owning School: Engineering
  • Teaching Location: Newcastle City Campus
Semesters
Semester 1 Credit Value: 10
ECTS Credits: 5.0

Aims

This module gives the student an understanding of design for test methodologies and to introduce them to the VHDL Language and the design tools based on VHDL. The course covers the following topics: techniques for ATPG, Fault Simulation and Testability Analysis for VLSI circuits; methodologies for designing testable circuits; VHDL Language and design tools based on the VHDL Language.

Outline Of Syllabus

Introduction:
Importance of test; why electronic systems malfunction/fail; difficulty of testing VLSI circuits and systems.
Test Engineers Tool Kit:
Automatic test pattern generation: what it is, the basic issues related to test pattern generation, a description of the path sensitation method and examples of its use.
Fault simulation: what it is, the fault simulation process, a description of fault simulations methods (Parallel and Concurrent) and examples of their use.
Testability Analysis: what it is, testability measurement parameters, a description of a testability analyser and examples of it use.
Design for Testability(DFT):
What is design for testability; the impact of the incorporation of DFT into a design; structured approach to DFT; objectives of Built in Self Test (BIST); essential components of a BIST system and its problematic issues; example of a BIST scheme.
Hardware Description Languages:
Introduction to VHDL, behavioural modelling of the commonly used functional blocks in a digital design and simulation in a VHDL environment; design of a test bench.

Teaching Methods

Please note that module leaders are reviewing the module teaching and assessment methods for Semester 2 modules, in light of the Covid-19 restrictions. There may also be a few further changes to Semester 1 modules. Final information will be available by the end of August 2020 in for Semester 1 modules and the end of October 2020 for Semester 2 modules.

Teaching Activities
Category Activity Number Length Student Hours Comment
Guided Independent StudyAssessment preparation and completion12:002:00Final exam
Guided Independent StudyAssessment preparation and completion240:3012:00Revision for final exam
Scheduled Learning And Teaching ActivitiesLecture241:0024:00N/A
Scheduled Learning And Teaching ActivitiesPractical51:005:00VHDL
Guided Independent StudyIndependent study157:0057:00Review Recap lectures; solve tutorial problems; understand concepts/principles outlined in lectures
Total100:00
Teaching Rationale And Relationship

Lectures provide the core material and guidance for further reading and subsequent advancement of knowledge about the design and test of VLSI circuits and systems.

Assessment Methods

Please note that module leaders are reviewing the module teaching and assessment methods for Semester 2 modules, in light of the Covid-19 restrictions. There may also be a few further changes to Semester 1 modules. Final information will be available by the end of August 2020 in for Semester 1 modules and the end of October 2020 for Semester 2 modules.

The format of resits will be determined by the Board of Examiners

Exams
Description Length Semester When Set Percentage Comment
Written Examination1201A100N/A
Exam Pairings
Module Code Module Title Semester Comment
1N/A
Assessment Rationale And Relationship

The closed book examination allows the students to demonstrate their problem solving skills together with their closed knowledge and understanding of the subject matter outlined in the lectures.

Semester 1 Study Abroad students will be able to sit the assessment earlier.

Reading Lists

Timetable