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Module

EEE3007 : Design and Test of Digital Systems (Inactive)

  • Inactive for Year: 2020/21
  • Module Leader(s): Dr Gordon Russell
  • Owning School: Engineering
  • Teaching Location: Newcastle City Campus
Semesters
Semester 1 Credit Value: 10
ECTS Credits: 5.0

Aims

This module gives the student an understanding of design for test methodologies and to introduce them to the VHDL Language and the design tools based on VHDL. The course covers the following topics: techniques for ATPG, Fault Simulation and Testability Analysis for VLSI circuits; methodologies for designing testable circuits; VHDL Language and design tools based on the VHDL Language.

Outline Of Syllabus

Introduction:
Importance of test; why electronic systems malfunction/fail; difficulty of testing VLSI circuits and systems.
Test Engineers Tool Kit:
Automatic test pattern generation: what it is, the basic issues related to test pattern generation, a description of the path sensitation method and examples of its use.
Fault simulation: what it is, the fault simulation process, a description of fault simulations methods (Parallel and Concurrent) and examples of their use.
Testability Analysis: what it is, testability measurement parameters, a description of a testability analyser and examples of it use.
Design for Testability(DFT):
What is design for testability; the impact of the incorporation of DFT into a design; structured approach to DFT; objectives of Built in Self Test (BIST); essential components of a BIST system and its problematic issues; example of a BIST scheme.
Hardware Description Languages:
Introduction to VHDL, behavioural modelling of the commonly used functional blocks in a digital design and simulation in a VHDL environment; design of a test bench.

Teaching Methods

Module leaders are revising this content in light of the Covid 19 restrictions.
Revised and approved detail information will be available by 17 August.

Assessment Methods

Module leaders are revising this content in light of the Covid 19 restrictions.
Revised and approved detail information will be available by 17 August.

Reading Lists

Timetable