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Module

EEE8020 : Advanced VLSI Design (Inactive)

  • Inactive for Year: 2022/23
  • Module Leader(s): Professor Satnam Dlay
  • Lecturer: Professor Alex Yakovlev
  • Owning School: Engineering
  • Teaching Location: Newcastle City Campus
Semesters
Semester 2 Credit Value: 15
ECTS Credits: 8.0

Aims

To introduce the students to the fundamentals of VLSI design and provide them with the essential knowledge about the main themes, so that, in future, the studnets will be able to readily apply this knowledge in industry or research or furher in by self study.

Outline Of Syllabus

Transistor topology; transistor equations; CMOS process steps; fabrication; yield; design rules for custom layout; alternative inverter. Complex gates; pseudo NMOS; dynamic logic; dynamic cascaded logic; domino logic; 2 and 4 phase logic; pass transistor logic. Control and timing; synchronous and asynchronous; self-timed systems; multi-phase clocks; register transfer; examples of ALU, shifters, and registers. Layout, hand layout, graphical layout, low-level language; design rule checking; stick diagrams; placement of cells; simulation of design; function generation from masks; test patterngeneration; high-level languages; structured design methodology for VLSI; hierarchical design techniques and examples. Serial addition; bit-serial multipliers; systoilc arrays; analogue voltagedividers; current mirrors; differential amplifiers; wide range amplifiers. Effects of scaling circuit dimensions; physical limits to develop fabrication. Optional extended course work for final year students, using VLSI design software to produce a chip to meet a given specification; the chip may be fabricated if the design is successful. To study the different stages in the design of integrated chip using VLSI design software. The design is to meet a given specification. Alternative high level structures, analogue function for specific applications.

Case Study Lecture.

Design of MSI chip using proprietary CAD system; use of circuit description language; layout considerations.

Teaching Methods

Teaching Activities
Category Activity Number Length Student Hours Comment
Scheduled Learning And Teaching ActivitiesLecture361:0036:00N/A
Guided Independent StudyAssessment preparation and completion13:003:00Final exam
Guided Independent StudyAssessment preparation and completion360:3018:00Revision for final exam
Guided Independent StudyIndependent study193:0093:00Reviewing lecture notes; general reading
Total150:00
Jointly Taught With
Code Title
EEE3012Integrated Circuit Design
Teaching Rationale And Relationship

Lectures provide core material and guidance for further reading, problem solving practice is integrated into lecture structure

Assessment Methods

The format of resits will be determined by the Board of Examiners

Exams
Description Length Semester When Set Percentage Comment
Written Examination1802A100N/A
Exam Pairings
Module Code Module Title Semester Comment
2N/A
Assessment Rationale And Relationship

The examination provides the opportunity for the student to demonstrate their understanding of the course material. The problem solving aspects of the assessment enable the student to demonstrate that they are able to apply this understanding and their analysis and synthesis skills to novel situations

Reading Lists

Timetable