EEE2013 : Digital Electronics
- Offered for Year: 2021/22
- Module Leader(s): Dr Fei Xia
- Owning School: Engineering
- Teaching Location: Newcastle City Campus
Semesters
| Semester 2 Credit Value: | 10 |
| ECTS Credits: | 5.0 |
Aims
To enable students to understand the essential principles of digital logic systems as used for control, communications and information processing.
To enable the student to design such systems.
To study the operation and performance of computer arithmetic circuits, synchronous and asynchronous sequential logic circuits.
Outline Of Syllabus
1. Logic Design and VHDL
Review of techniques for logic design, from discrete logic gates to ASICs; The VHDL language as a tool for digital design; FPGA and PLA architectures.
2. Arithmetic Circuits
Combinational logic circuits for the parallel adder; carry propagation; carry look-ahead; subtraction; logic functions; the ALU; multiplication and shifting; serial multipliers: parallel and carry save methods.
3. Sequential Logic
Synchronous systems
Finite state machines; state assignment; synthesis of synchronous FSMs; implementation methods; memory and combinational logic; examples of implementation of controllers and algorithms.
Asynchronous systems
Fundamental mode; implementation of a primitive flow table; races; metastability and synchronisation failure.
Teaching Methods
Teaching Activities
| Category | Activity | Number | Length | Student Hours | Comment |
|---|---|---|---|---|---|
| Scheduled Learning And Teaching Activities | Lecture | 22 | 1:00 | 22:00 | 2x1hr lectures per week over 11 weeks |
| Guided Independent Study | Assessment preparation and completion | 1 | 5:00 | 5:00 | Writing of summatively assessed lab report. |
| Guided Independent Study | Assessment preparation and completion | 1 | 1:00 | 1:00 | Formatively assessed online NUMBAS test in middle of semester |
| Guided Independent Study | Assessment preparation and completion | 1 | 5:00 | 5:00 | Revision for online NUMBAS test |
| Guided Independent Study | Assessment preparation and completion | 1 | 2:00 | 2:00 | Final Exam in Assessment Period |
| Guided Independent Study | Assessment preparation and completion | 15 | 1:00 | 15:00 | Revision for final exam |
| Scheduled Learning And Teaching Activities | Practical | 1 | 3:00 | 3:00 | One three-hour practical lab session on using VHDL for FPGA programming. |
| Structured Guided Learning | Structured research and reading activities | 11 | 1:00 | 11:00 | Reading activity to supplement knowledge of material taught in each week. |
| Scheduled Learning And Teaching Activities | Workshops | 7 | 1:00 | 7:00 | One online synchronous tutorial per week from second week, covering tutorial sheets. |
| Guided Independent Study | Independent study | 26 | 1:00 | 26:00 | Reviewing lecture notes; general reading |
| Scheduled Learning And Teaching Activities | Scheduled on-line contact time | 3 | 1:00 | 3:00 | One online synchronous review session per week, reviewing lecture material. |
| Total | 100:00 |
Teaching Rationale And Relationship
Lectures provides the core material and synchronous review sessions give students the opportunity to query material taught in that week. Face-to-face lectures can be replaced with online synchronous sessions support by non-synchronous videos if the public health situation requires it.
Problem solving is introduced and practiced through synchronous tutorial sessions.
Laboratory sessions provide an opportunity to gain practical experience and validate the theory introduced in lectures. These sessions can be immediately replaced with a simulation-based experiment, supported by synchronous drop-in sessions if the public health situation requires it.
Assessment Methods
The format of resits will be determined by the Board of Examiners
Exams
| Description | Length | Semester | When Set | Percentage | Comment |
|---|---|---|---|---|---|
| Written Examination | 120 | 2 | A | 85 | Closed-Book Exam |
Other Assessment
| Description | Semester | When Set | Percentage | Comment |
|---|---|---|---|---|
| Practical/lab report | 2 | M | 15 | Lab Report with a maximum of 1000 words. |
Formative Assessments
| Description | Semester | When Set | Comment |
|---|---|---|---|
| Computer assessment | 2 | M | In case of pandemic emergency preventing the lab sessions on campus, this element may be assessed at 15% in place of lab report. |
Assessment Rationale And Relationship
The examination allows students to demonstrate their ability to solve engineering problems focused digital electronics, based on the knowledge and methodology presented in the course material. The laboratory report assesses technical writing skills and provides the opportunity for the students to demonstrate the hardware programming skills taught in the course material. The formative computer-based assessment will assess the students’ current level of understanding of the material taught up to the middle of the semester and provide useful feedback on strengths and weaknesses.
In case where on campus labs are not possible, this component will not be assessed at 15%, to be replaced by the NUMBAS assessment below.
Reading Lists
Timetable
- Timetable Website: www.ncl.ac.uk/timetable/
- EEE2013's Timetable