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ENG2025 : Digital Electronics

  • Offered for Year: 2023/24
  • Module Leader(s): Dr Domenico Balsamo
  • Owning School: Engineering
  • Teaching Location: Newcastle City Campus
Semester 2 Credit Value: 10
ECTS Credits: 5.0


This module will provide know-how on designing digital circuits and systems. Students will learn to critically analyse and evaluate combinatorial circuits and synchronous and asynchronous sequential circuits from the designer's point of view. This module will also focus on learning computer-aided digital design techniques and hardware description languages (VHDL), mainly for programmable logic devices, logic synthesis and simulation. At the end of the course, the student will be able to design digital circuits and systems, including computer arithmetic circuits and synchronous and asynchronous sequential logic circuits based on programmable logic.

Outline Of Syllabus

INTRODUCTION: Introduction to digital circuits.

COMBINATORIAL LOGIC: Basic arithmetic and standard combinational logic circuits, including adders (i.e., carry propagation and carry look-ahead) and multipliers (i.e., serial and parallel multipliers and carry save methods) and other operations required in Programmable Logic Arrays (PLA) and Arithmetic-Logic Unit (ALU).

SYNCHRONOUS SEQUENTIAL LOGIC: Standard synchronous elements: registers, shift registers, and counters. Examples of the design of synchronous logic circuits containing registers, shift registers and counters. Examples of the design of synchronous sequential circuits based on combinational logic with a feedback loop using memory elements (i.e., flip-flops).

Sequential logic systems, including synthesis of Finite State Machines (FSMs).

ASYNCHRONOUS SEQUENTIAL LOGIC: Asynchronous sequential circuit design as a combinational circuit with direct feedback. Constraints for correct use of asynchronous design and techniques aimed at a priori removal of undesired behaviours (primitive flow table, races, metastability and synchronisation failure).

Asynchronous FSM and description of their behaviour using a state diagram and state table.

Design and analysis of asynchronous sequential logic circuits. Asynchronous sequential logic circuits for binary memories: latches and delays.

VHDL as a design tool: Entity and architectures. Concurrent statements. Structural descriptions and components. VHDL operators. Arithmetic's in VHDL. Processes and sequential constructs. Sequential logic and registers. Description style for synthesisable VHDL. RTL descriptions. Finite State Machines. Design examples. Laboratory sessions: design digital systems with CAD EDA tools (EDA Playground).

Teaching Methods

Teaching Activities
Category Activity Number Length Student Hours Comment
Guided Independent StudyAssessment preparation and completion111:0011:00Open book assignment (problem solving) (9 hours of budgeted prep time +1 hour NUMBAS assessment
Scheduled Learning And Teaching ActivitiesLecture221:0022:002x1hr lectures per week over 11 weeks
Guided Independent StudyAssessment preparation and completion12:002:00Written exam
Guided Independent StudyAssessment preparation and completion280:3014:00Revision for Exam
Guided Independent StudyAssessment preparation and completion401:0040:00General reading; reviewing lecture notes; solving practical problems
Scheduled Learning And Teaching ActivitiesPractical111:0011:00VHDL hardware description language
Teaching Rationale And Relationship

Besides regular class activity in which slides (whose PDF printouts are available from the course's CANVAS page before lectures) are used and discussed during class hours, allowing students to focus on the discussed concepts and take notes. A relevant part of the course will be spent in a computer cluster to learn hardware description languages and digital design tools. Laboratory sessions and tutorials will focus on practising VHDL using CAD EDA tools.

Assessment Methods

The format of resits will be determined by the Board of Examiners

Description Length Semester When Set Percentage Comment
Written Examination1202A80Exam workload 2 hours.
Other Assessment
Description Semester When Set Percentage Comment
Prob solv exercises2M20VHDL assignment
Assessment Rationale And Relationship

The examination allows the student to demonstrate their understanding of the course material. The VHDL assignment enables students to demonstrate that they can apply their digital design techniques knowledge and their analysis and synthesis skills using computer-aided and hardware description languages. The in-course assessments provide the opportunity for students to demonstrate their abilities under open-book conditions.

Reading Lists