ENG2025 : Digital Electronics
- Offered for Year: 2025/26
- Module Leader(s): Dr Domenico Balsamo
- Owning School: Engineering
- Teaching Location: Newcastle City Campus
Semesters
Your programme is made up of credits, the total differs on programme to programme.
| Semester 2 Credit Value: | 10 |
| ECTS Credits: | 5.0 |
| European Credit Transfer System | |
Aims
This module will provide know-how on designing digital circuits and systems. Students will learn to critically evaluate combinatorial and sequential circuits from the designer's point of view. This module will also focus on experiencing computer-aided digital design techniques and hardware description languages (VHDL), mainly for programmable logic devices, logic synthesis and simulation. At the end of the module, students will be able to design digital circuits and systems, including computer arithmetic circuits and synchronous and asynchronous sequential logic circuits based on programmable logic.
Outline Of Syllabus
Students will be asked to bring curiosity about hardware design. Together, we will develop the ability to design standard arithmetic and combinational logic circuits, move to synchronous and asynchronous sequential logic, and address finite state machines.
In particular, one important aspect covered in this module is handling hardware description language such as VHDL. These are used to describe, simulate, and create hardware for digital circuits such that these can be simulated before being implemented in the hardware.
Upon completing this module, which spans one semester, students will become familiar with hardware description languages such as VDHL and gain experience designing the core building blocks used in digital electronics.
Through these outcomes, students will more naturally learn other hardware programming languages (e.g., Verilog) that are useful for career advancement.
Teaching Methods
Teaching Activities
| Category | Activity | Number | Length | Student Hours | Comment |
|---|---|---|---|---|---|
| Scheduled Learning And Teaching Activities | Lecture | 22 | 1:00 | 22:00 | 2x1hr lectures per week over 11 weeks |
| Guided Independent Study | Assessment preparation and completion | 1 | 2:00 | 2:00 | Written exam |
| Guided Independent Study | Assessment preparation and completion | 1 | 8:00 | 8:00 | Revision for Exam |
| Guided Independent Study | Assessment preparation and completion | 40 | 1:00 | 40:00 | General reading; reviewing lecture notes; solving practical problems including formative assessment |
| Guided Independent Study | Assessment preparation and completion | 1 | 12:00 | 12:00 | Open book assignment (problem solving) (12 hours of budgeted prep time) |
| Scheduled Learning And Teaching Activities | Practical | 8 | 2:00 | 16:00 | VHDL hardware description language |
| Total | 100:00 |
Teaching Rationale And Relationship
Besides regular class activity in which slides (whose PDF printouts are available from the course's CANVAS page before lectures) are used and discussed during class hours, allowing students to focus on the discussed concepts and take notes. A relevant part of the course will be spent in a computer cluster to learn hardware description languages and digital design tools. Laboratory sessions and tutorials will focus on practising VHDL using CAD EDA tools.
Assessment Methods
The format of resits will be determined by the Board of Examiners
Exams
| Description | Length | Semester | When Set | Percentage | Comment |
|---|---|---|---|---|---|
| Written Examination | 120 | 2 | A | 75 | Exam workload 2 hours. |
Other Assessment
| Description | Semester | When Set | Percentage | Comment |
|---|---|---|---|---|
| Practical/lab report | 2 | M | 25 | VHDL assignment |
Formative Assessments
Formative Assessment is an assessment which develops your skills in being assessed, allows for you to receive feedback, and prepares you for being assessed. However, it does not count to your final mark.
| Description | Semester | When Set | Comment |
|---|---|---|---|
| Prob solv exercises | 2 | M | Problem solving exercise on combinatorial logic in VHDL. |
| Prob solv exercises | 2 | M | Problem solving exercise on structural level design in VHDL. |
| Prob solv exercises | 2 | M | Problem solving exercise on using the concept of process in VHDL. |
| Prob solv exercises | 2 | M | Problem solving exercise on latches and flip-flops in VHDL. |
| Prob solv exercises | 2 | M | Problem solving exercise on registers and counters in VHDL. |
Assessment Rationale And Relationship
The examination allows the student to demonstrate their understanding of the course material. The VHDL assignment enables students to demonstrate that they can apply their digital design techniques knowledge and their analysis and synthesis skills using computer-aided and hardware description languages. The formative problem solving exercises provide the opportunity for students to demonstrate their abilities in using VHDL.
Exam (C1, C2).
Practical/Lab Report 1 (VHDL assessment) (C3, M3, C6).
Reading Lists
Timetable
- Timetable Website: www.ncl.ac.uk/timetable/
- ENG2025's Timetable